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36 june 2007 rev 1 1/36 LIS202DL mems motion sensor 2-axis - 2g/8g smart digital output ?piccolo? accelerometer feature 2.16v to 3.6v supply voltage 1.8v compatible ios <1mw power consumption 2g/ 8g dynamically selectable full-scale i 2 c/spi digital output interface programmable interrupt generator click and double click recognition embedded high pass filter embedded self test 10000g high shock survivability ecopack? rohs and ?green? compliant (see section 9 ) description the LIS202DL is an ultra compact low-power two axes linear accelerometer. it includes a sensing element and an ic interface able to provide the measured acceleration to the external world through i 2 c/spi serial interface. the sensing element, capable of detecting the acceleration, is manufactured using a dedicated process developed by st to produce inertial sensors and actuators in silicon. the ic interface is manufactured using a cmos process that allows to design a dedicated circuit which is trimmed to better match the sensing element characteristics. the LIS202DL has dynamically user selectable full scales of 2g/ 8g and it is capable of measuring accelerations with an output data rate of 100hz or 400hz. a self-test capability allows the user to check the functioning of the sensor in the final application. the device may be configured to generate inertial wake-up interrupt signals when a programmable acceleration threshold is crossed at least in one of the two axes. thresholds and timing of interrupt generators are programmable by the end user on the fly. the LIS202DL is available in plastic thin land grid array package (tlga) and it is guaranteed to operate over an extended temperature range from -40c to +85c. the LIS202DL belongs to a family of products suitable for a variety of applications: ? motion activated functions ? gaming and virtual reality input devices ? vibration monitoring and compensation lga-14 (3x5x0.9mm) table 1. device summary part number temp range, cpackage packing LIS202DL -40 to +85 lga tray LIS202DLtr -40 to +85 lga tape and reel www.st.com
contents LIS202DL 2/36 contents 1 block diagram & pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4.2 zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4.3 self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4.4 click and double click recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 ic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 i2c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.1 i2c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.3 spi read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
LIS202DL contents 3/36 7.1 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.2 ctrl_reg1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.3 ctrl_reg2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.4 ctrl_reg3 [interrupt ctrl register] (22h) . . . . . . . . . . . . . . . . . . . . . . 22 7.5 hp_filter_reset (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.6 status_reg (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.7 out_x (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.8 out_y (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.9 wu_cfg_1 (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.10 wu_src_1 (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.11 wu_ths_1 (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.12 wu_duration_1 (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.13 wu_cfg_2 (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.14 wu_src_2 (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.15 wu_ths_2 (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.16 wu_duration_2 (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.17 click_cfg (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.18 click_src (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.19 click_thsy_x (3bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.20 click_timelimit (3dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.21 click_latency (3eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.22 click_window (3fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 typical performance characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.1 mechanical characteristics at 25c . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.2 mechanical characteristics derived from measurement in the -40c to +85c temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.3 electro-mechanical characteristics at 25c . . . . . . . . . . . . . . . . . . . . . . . 33 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
block diagram & pin description LIS202DL 4/36 1 block diagram & pin description 1.1 block diagram figure 1. block diagram 1.2 pin description figure 2. pin connection charge amplifier mux y+ y- a x+ x- i 2 c spi cs scl/spc sda/sdo/sdi sdo control logic & interrupt gen. int 1 clock trimming circuits reference self test control logic a/d converter int 2 table 2. pin description pin# name function 1 vdd_io power supply for i/o pins 2 gnd 0v supply 3 reserved connect to vdd 4 gnd 0v supply 5 gnd 0v supply 6 vdd power supply 1 13 8 6 1 bottom view 13 8 6 top view x y
LIS202DL block diagram & pin description 5/36 7cs spi enable i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) 8 int 1 inertial interrupt 1 9 int 2 inertial interrupt 2 10 gnd 0v supply 11 reserved connect to gnd 12 sdo spi serial data output i 2 c less significant bit of the device address 13 sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 14 scl spc i 2 c serial clock (scl) spi serial port clock (spc) table 2. pin description (continued) pin# name function
mechanical and electrical specifications LIS202DL 6/36 2 mechanical and electrical specifications 2.1 mechanical characteristics (all the parameters are specified @ vdd=2.5v, t = 25c unless otherwise noted) table 3. mechanical characteristics (1) symbol parameter test conditions min. typ. (2) max. unit fs measurement range (3) fs bit set to 0 2.0 2.3 g fs bit set to 1 8.0 9.2 so sensitivity fs bit set to 0 16.2 18 19.8 mg/digit fs bit set to 1 64.8 72 79.2 tcso sensitivity change vs temperature fs bit set to 0 0.01 %/c ty o f f typical zero-g level offset accuracy (4),(5) fs bit set to 0 40 mg fs bit set to 1 60 mg tcoff zero-g level change vs temperature max delta from 25c 0.5 mg/c vst self test output change (6),(7),(8) fs bit set to 0 stp bit used x axis vdd=2.16v to 3.6v -32 -3 lsb fs bit set to 0 stp bit used y axis vdd=2.16v to 3.6v 332lsb bw system bandwidth (9) odr/2 hz top operating temperature range -40 +85 c wh product weight 30 mgram 1. the product is factory calibrated at 2.5v. the device can be used from 2.16v to 3.6v 2. typical specificat ions are not guaranteed 3. verified by wafer level test and measur ement of initial offset and sensitivity 4. typical zero-g level offset value after msl3 preconditioning 5. offset can be eliminated by enabl ing the built-in high pass filter 6. if stm bit is used values change in sign for all axes 7. self test output changes with the power supply. self test ?output change? is defined as output[lsb] (self-test bit on ctrl_reg1=1) -output[lsb] (self-test bit on ctrl_reg1=0) . 1lsb=4.6g/256 at 8bit representation, 2.3g full-scale 8. output data reach 99% of final value after 3/od r when enabling self-test mode due to device filtering 9. odr is output data rate. refer to table 3 for specifications
LIS202DL mechanical and electrical specifications 7/36 2.2 electrical characteristics (all the parameters are specified @ vdd=2.5v, t= 25c unless otherwise noted) table 4. electrical characteristics (1) symbol parameter test conditions min. typ. (2) max. unit vdd supply voltage 2.16 2.5 3.6 v vdd_io i/o pins supply voltage (3) 1.71 vdd+0.1 v idd supply current t = 25c, odr=100hz 0.3 0.4 ma iddpdn current consumption in power-down mode t = 25c 1 5 a vih digital high level input voltage 0.8*vdd _io v vil digital low level input voltage 0.2*vdd _io v voh high level output voltage 0.9*vdd _io v vol low level output voltage 0.1*vdd _io v odr output data rate dr=0 100 hz dr=1 400 bw system bandwidth (4) odr/2 hz ton turn-on time (5) 3/odr s top operating temperature range -40 +85 c 1. the product is factory calibrated at 2.5v. the device can be used from 2.16v to 3.6v 2. typical specification are not guaranteed 3. it is possible to remove vdd maintaining vdd_io withou t blocking the communication busse s, in this condition the measurement chain is powered off. 4. filter cut-off frequency 5. time to obtain valid data after exiting power-down mode
mechanical and electrical specifications LIS202DL 8/36 2.3 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: supply voltage on any pin should never exceed 6.0v table 5. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 6 v vdd_io i/o pins supply voltage -0.3 to 6 v vin input voltage on any control pin (cs, scl/spc, sda/sdi/sdo) -0.3 to vdd_io +0.3 v a pow acceleration (any axis, powered, vdd=2.5v) 3000g for 0.5 ms 10000g for 0.1 ms a unp acceleration (any axis, unpowered) 3000g for 0.5 ms 10000g for 0.1 ms t op operating temperature range -40 to +85 c t stg storage temperature range -40 to +125 c esd electrostatic discharge protection 4.0 (hbm) kv 200 (mm) v 1500 (cdm) v this is a mechanical shock sensitive device, improper handling can cause permanent damages to the part this is an esd sensitive device, improper handling can cause permanent damages to the part
LIS202DL mechanical and electrical specifications 9/36 2.4 terminology 2.4.1 sensitivity sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g acceleration to it. as the sensor can measur e dc accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. by doing so, 1g acceleration is applied to the sensor. subtracting the larger output value from the smaller one and dividing the result by 2 leads to the actual sensitivity of the sensor. this value changes very little over temperature and also time. the sensitivity tolerance describes the range of sensitivities of a large population of sensors. 2.4.2 zero-g level zero-g level offset (tyoff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. a sensor in a steady state on a horizontal surface will measure 0g in x axis and 0g in y axis. the output is ideally in the middle of the dynamic range of the sensor (content of out registers 00h, data expressed as 2?s complement number). a deviation from ideal value in this case is called zero-g offset. offset is to some extent a result of stress to mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit boar d or exposing it to extensive mechanical stress. offset changes little over temperature, see ?zero-g level change vs. temperature?. the zero-g level tolerance (tyoff) describes the standard deviation of the range of zero-g levels of a population of sensors. 2.4.3 self test self test allows to check the sensor functionality without moving it. the self test function is off when the self-test bit of ctrl_reg1 (control register 1) is programmed to ?0?. when the self- test bit of ctrl_reg1 is programmed to ?1? an actuation force is applied to the sensor, simulating a definite input acceleration. in this case the sensor outputs will exhibit a change in their dc levels which are related to the sele cted full scale through the device sensitivity. when self test is activated, the device output level is given by the algebric sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. if the output signals change within the amplitude specified inside ta b l e 3 , then the sensor is working properly and the parameters of the interface chip are within the defined specifications. 2.4.4 click and double click recognition the click and double click recognition functions help to create man-machine interface with little software overload. the device can be configured to output an interrupt signal on dedicated pin when tapped in any direction. if the sensor is exposed to a single input stimulus it generates an interrupt request on inertial interrupt pins (int1 and/or int2). a more advanced feature allows to generate an interrupt request when a ?double click? stimulus is applied. a programmable time between the two events allows a flexible adoption to the application requirements. mouse-button like application like clicks and double clicks can be implemented. this function can be fully programmed by the user in terms of expected amplitude and timing of the stimuli.
functionality LIS202DL 10/36 3 functionality the LIS202DL is an ultracompact, low-power, digital output 2-axis linear accelerometer packaged in a lga package. the complete device includes a sensing element and an ic interface able to take the information from the sensing element and to provide a signal to the external world through an i 2 c/spi serial interface. 3.1 sensing element a proprietary process is used to create a surface micro-machined accelerometer. the technology allows to carry out suspended s ilicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. to be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. when an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacit ive half-bridge. this imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor. at steady state the nominal value of the capacitors are few pf and when an acceleration is applied the maximum variation of the capacitive load is in pf range. 3.2 ic interface the complete measurement chain is composed by a low-noise capacitive amplifier which converts the capacitive unbalancing of the mems sensor into an analog voltage that is finally available to the user by analog-to-digital converters. the acceleration data may be accessed through an i 2 c/spi interface thus making the device particularly suitable for direct interfacing with a microcontroller. the LIS202DL features a data-ready signal (rdy) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in the digital system that uses the device. the LIS202DL may also be configured to generate an inertial wake-up interrupt signal accordingly to a programmed acceleration event along the enabled axes. 3.3 factory calibration the ic interface is factory calibrated for sensitivity (so) and zero-g level (tyoff). the trimming values are stored inside the device in a non volatile memory. any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the normal operation. this allows to use the device without further calibration.
LIS202DL application hints 11/36 4 application hints figure 3. LIS202DL electrical connection the device core is supplied through vdd line while the i/o pads are supplied through vdd_io line. power supply decoupling capacitors (100 nf ceramic, 10 f al) should be placed as near as possible to the pin 6 of the device (common design practice). all the voltage and ground supplies must be present at the same time to have proper behavior of the ic ( figure 3: LIS202DL electrical connection ). it is possible to remove vdd maintaining vdd_io without blocking the co mmunication busses, in this condition the measurement chain is powered off. the functionality of the device and the measured acceleration data is selectable and accessible through the i 2 c/spi interface.when using the i 2 c, cs must be tied high while sdo must be left floating. the functions, the threshold an the timing of the two interrupt pins (int 1 and int 2) can be completely programmed by the user though the i 2 c/spi interface. 4.1 soldering information the lga package is compliant with the ecopack, rohs and ?green? standard. it is qualified for soldering heat resistance according to jedec j-std-020c. pin #1 indicator is electrically connected to pin 1. leave pin 1 indicator unconnected during soldering. land pattern and soldering recommendation are available at www.st.com/mems . 6 8 13 1 top view cs 10uf vdd 100nf gnd vdd_io sdo sda/sdi/sdo int_1 int_2 scl/spc digital signal from/to signal controller.signal?s levels are defined by proper selection of vdd_io 1 13 8 6 top view x y direction of the detectable accelerations
digital interfaces LIS202DL 12/36 5 digital interfaces the registers embedded inside the LIS202DL may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw configured to operate either in 3-wire or 4-wire interface mode. the serial interfaces are mapped onto the same pads. to select/exploit the i 2 c interface, cs line must be tied high (i.e connected to vdd_io). 5.1 i 2 c serial interface the LIS202DL i 2 c is a bus slave. the i 2 c is employed to write the data into the registers whose content can also be read back. the relevant i 2 c terminology is given in the table below. there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. both the lines are connected to vdd_io through a pull-up resistor embedded inside the LIS202DL. when the bus is free both the lines are high. the i 2 c interface is compliant with fast mode (400 khz) i 2 c standards as well as the normal mode. table 6. serial interface pin description pin name pin description cs spi enable i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) scl/spc i 2 c serial clock (scl) spi serial port clock (spc) sda/sdi/sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sdo spi serial da ta output (sdo) table 7. serial interface pin description term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master
LIS202DL digital interfaces 13/36 5.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high to low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the slave address (sad) associated to the LIS202DL is 001110xb. sdo pad can be used to modify less significant bit of the device address. if sdo pad is connected to voltage supply lsb is ?1? (address 0011101b) else if sdo pad is connected to ground lsb value is ?0? (address 0011100b). this solution permits to connect and address two different accelerometer to the same i 2 c lines. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data has been received. the i 2 c embedded inside the LIS202DL behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a salve address is sent, once a slave acknowledge (sak) has bee n returned, a 8-bit sub-addre ss will be transmitted: the 7 lsb represent the actual register address while the msb enables address auto increment. if the msb of the sub field is 1, the sub (regis ter address) will be auto matically increment to allow multiple data read/write. the slave address is completed with a read/write bit. if the bit was ?1? (read), a repeated start (sr) condition will have to be issued after the two sub-addr ess bytes; if the bit is ?0? (write) the master will transmit to the slave with di rection unchanged.
digital interfaces LIS202DL 14/36 transfer when master is writing one byte to slave: transfer when master is writing multiple bytes to slave: transfer when master is receiving (reading) one byte of data from slave: transfer when master is receiving (reading) multiple bytes of data from slave: data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver can?t receive another complete byte of data until it has performed some other function, it can hold the clock line, scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver doesn?t acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left high by the slave. the master can then abort the transfer. a low to high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. in other words, sub(7) must be equal to 1 while sub(6-0) represents the address of first register to read. in the presented communication format mak is master acknowledge and nmak is no master acknowledge. 5.2 spi bus interface the LIS202DL spi is a bus slave. the spi allows to write and read the registers of the device. the serial interface interacts with the outside world with 4 wires: cs , spc , sdi and sdo . master st sad + w sub data sp slave sak sak sak master st sad + w sub data data sp slave sak sak sak sak master st sad+w sub sr sad+r nmak sp slave sak sak sak data master st sad + w sub sr sad + r mak slave sak sak sak data master mak nmak sp s l a ve data data
LIS202DL digital interfaces 15/36 figure 4. read & write protocol cs is the serial port enable and it is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port data input and output. those lines are driven at the falling edge of spc and should be captured at the rising edge of spc . both the read register and write register commands are completed in 16 clock pulses or in multiple of 8 in case of mu ltiple byte read/write. bit durati on is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the falling edge of cs while the last bit (bit 15, bit 23, ...) starts at the last falling edge of spc just before the rising edge of cs . bit 0 : rw bit. when 0, the data di(7:0) is written into the device. when 1, the data do(7:0) from the device is read. in latter case, the chip will drive sdo at the start of bit 8. bit 1 : ms bit. when 0, the address will remain unch anged in multiple r ead/write commands. when 1, the address will be auto increment ed in multiple r ead/write commands. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (wri te mode). this is the data that will be written into the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the da ta that will be read from the device (msb first). in multiple read/write comman ds further blocks of 8 clock periods will be added. when ms bit is 0 the address used to read/write data remains the same for every block. when ms bit is 1 the address used to read/write data is incremented at every block. the function and the behavior of sdi and sdo remain unchanged. cs spc sdi sdo rw ad5 ad4 ad3 ad2 ad1 ad0 di7di6di5di4di3di2di1di0 do7do6do5do4do3do2do1do0 ms
digital interfaces LIS202DL 16/36 5.2.1 spi read figure 5. spi read protocol the spi read command is performed with 16 clock pulses. multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the da ta that will be read from the device (msb first). bit 16-... : data do(...-8). further da ta in multiple byte reading. figure 6. multiple bytes spi read protocol (2 bytes example) 5.2.2 spi write figure 7. spi write protocol cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms cs spc sdi sdo rw do7do6do5do4do3do2do1do0 ad5 ad4 ad3 ad2 ad1 ad0 do15 do14 do13 do12 do11 do10 do9 do8 ms cs spc sdi rw di7 di6 di5 di4 di3 di2 di1 di0 ad5 ad4 ad3 ad2 ad1 ad0 ms
LIS202DL digital interfaces 17/36 the spi write command is performed with 16 cl ock pulses. multiple by te write command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : write bit. the value is 0. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple writing. bit 2 -7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (wri te mode). this is th e data that will be writ ten inside the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writing. figure 8. multiple bytes spi write protocol (2 bytes example) 5.2.3 spi read in 3-wires mode 3-wires mode is entered by setting to 1 bit sim (spi serial interface mode selection) in ctrl_reg2. figure 9. spi read protocoin 3-wires model the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the da ta that will be read from the device (msb first). multiple read command is also available in 3-wires mode. cs spc sdi rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 di15 di14 di13 di12 di11 di10 di9 di8 ms cs spc sdi/o rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms
register mapping LIS202DL 18/36 6 register mapping the table given below provides a listing of the 8 bit registers embedded in the device and the related address: table 8. register address map name type register address default comment hex binary reserved (do not modify) 00-0e reserved who_am_i r 0f 000 1111 00111011 dummy register reserved (do not modify) 10-1f reserved ctrl_reg1 rw 20 010 0000 00000111 ctrl_reg2 rw 21 010 0001 00000000 ctrl_reg3 rw 22 010 0010 00000000 hp_filter_reset r 23 010 0011 dummy dummy register reserved (do not modify) 24-26 reserved status_reg r 27 010 0111 00000000 -- r 28 010 1000 not used outx r 29 010 1001 output -- r 2a 010 1010 not used outy r 2b 010 1011 output -- r 2c 010 1100 not used -- r 2d 010 1101 not used reserved (do not modify) 2e-2f reserved wu_cfg_1 rw 30 011 0000 00000000 wu_src_1(ack1) r 31 011 0001 00000000 wu_ths_1 rw 32 011 0010 00000000 wu_duration_1 rw 33 011 0011 00000000 wu_cfg_2 rw 34 011 0100 00000000 wu_src_2 (ack2) r 35 011 0101 00000000 wu_ths_2 rw 36 011 0110 00000000 wu_duration_2 rw 37 011 0111 00000000 click_cfg rw 38 011 1000 00000000 click_src (ack) r 39 011 1001 00000000 -- 3a not used click_thsy_x rw 3b 011 1011 00000000 -- rw 3c 011 1100 00000000 not used
LIS202DL register mapping 19/36 registers marked as reserved must not be changed. the writing to those registers may cause permanent damages to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered-up. click_timelimit rw 3d 011 1101 00000000 click_latency rw 3e 011 1110 00000000 click_window rw 3f 011 1111 00000000 table 8. register address map name type register address default comment hex binary
register description LIS202DL 20/36 7 register description the device contains a set of registers which are used to control its behavior and to retrieve acceleration data. the registers address, made of 7 bits, is used to identify them and to write the data through serial interface. 7.1 who_am_i (0fh) device identification register. this register contains the device identifier that for LIS202DL is set to 3bh. 7.2 ctrl_reg1 (20h) dr bit allows to select the data rate at which acceleration samples are produced. the default value is 0 which corresponds to a data-r ate of 100hz. by changing the content of dr to ?1? the selected data-rate will be set equal to 400hz. pd bit allows to turn on the turn the device out of power-down mode. the device is in power- down mode when pd= ?0? (default value after boot). the device is in normal mode when pd is set to 1. table 9. register 00111011 table 10. register dr pd fs stp stm 0 (1) 1. bit to be set to ?0? for correct device functionality ye n x e n table 11. register description dr data rate selection. default value: 0 (0: 100 hz output data rate; 1: 400 hz output data rate) pd power down control. default value: 0 (0: power down mode; 1: active mode) fs full scale selection. default value: 0 (refer to ta bl e 2 for typical full scale value) stp, stm self test enable. default value: 00 (0: normal mode; 1: self test p, m enabled) ye n y axis enable. default value: 1 (0: y axis disabled; 1: y axis enabled) xen x axis enable. default value: 1 (0: x axis disabled; 1: x axis enabled)
LIS202DL register description 21/36 stp, stm bits are used to activate the self test function. when the bit is set to one, an output change will occur to the device outputs (refer to ta b l e 3 and ta b l e 4 for specification) thus allowing to check the functionality of the whole measurement chain. yen bit enables the generation of data ready signal for y-axis measurement channel when set to 1. the default value is 1. xen bit enables the generation of data ready signal for x-axis measurement channel when set to 1. the default value is 1. 7.3 ctrl_reg2 (21h) sim bit selects the spi serial interface mode. when sim is ?0? (default value) the 4-wire interface mode is selected. the data coming from the device are sent to sdo pad. in 3-wire interface mode output data are sent to sda_sdi pad. boot bit is used to refresh the content of internal registers stored in the flash memory block. at the device power up the content of the flash memory block is transferred to the internal registers related to trimming functions to permit a good behavior of the device itself. if for any reason the content of trimming registers was changed it is sufficient to use this bit to restore correct values. when boot bit is set to ?1? the content of internal flash is copied inside corresponding internal registers and it is used to calibrate the device. these values are factory trimmed and they are different for every accelerometer. they permit a good behavior of the device and normally they have not to be changed. at the end of the boot process the boot bit is set again to ?0?. fds bit enables (fds=1) or bypass (fds=0) the high pass filter in the signal chain of the sensor hp_coeff[2:1] . these bits are used to configure high-pass filter cut-off frequency ft. table 12. register sim boot -- fds hp wu2 hp wu1 hp_coeff2 hp_coeff1 table 13. register description sim spi serial interface mode selection. default value: 0 (0: 4-wire interface; 1: 3-wire interface) boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content) fds filtered data selection. default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register) hp wu2 high pass filter enabled for wakeup # 2. default value: 0 (0: filter bypassed; 1: filter enabled) hp wu1 high pass filter enabled for wake-up #1. default value: 0 (0: filter bypassed; 1: filter enabled) hp coeff2 hp coeff1 high pass filter cut-off frequency configuration. default value: 00 (see table below)
register description LIS202DL 22/36 7.4 ctrl_reg3 [interrupt ctrl register] (22h) table 14. truth table hpcoeff2,1 ft (hz) (odr=100 hz) ft (hz) (odr=400 hz) 00 2 8 01 1 4 10 0.5 2 11 0.25 1 table 15. register ihl pp_od i2cfg2 i2cfg1 i2cfg0 i1cfg2 i1cfg1 i1cfg0 table 16. register description ihl interrupt active high, low. default value 0. (0: active high; 1: active low) pp_od push-pull/open drain selection on interrupt pad. default value 0. (0: push-pull; 1: open drain) i2cfg2 i2cfg1 i2cfg0 data signal on int2 pad control bits. default value 000. (see table below) i1cfg2 i1cfg1 i1cfg0 data signal on int1 pad control bits. default value 000. (see table below) table 17. truth table i1(2)_cfg2 i1(2)_cfg1 i1 (2)_cfg0 int1(2) pad 0 0 0 gnd 001 wu_1 010 wu_2 0 1 1 wu_1 or wu_2 1 0 0 data ready 1 1 1 click interrupt
LIS202DL register description 23/36 7.5 hp_filter_reset (23h) dummy register. reading at this address zeroes instantaneously the content of the internal high pass-filter. if the high pass filter is enabled all two axes are instantaneously set to 0g. this allows to overcome the settling time of the high pass filter. 7.6 status_reg (27h) 7.7 out_x (29h) x axis output data. 7.8 out_y (2bh) table 18. register xyor -- yor xor yxda -- yda xda table 19. register description yxor x, y axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data has over written the previous one before it was read) yor y axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new data for the y-axis has overwritten the previous one) xor x axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new data for the x-axis has overwritten the previous one) yxda x, y axis new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) yda y axis new data available. default value: 0 (0: a new data for the y-axis is not yet available; 1: a new data for the y-axis is available) xda x axis new data available. default value: 0 (0: a new data for the x-axis is not yet available; 1: a new data for the x-axis is available) table 20. register xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 table 21. register yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0
register description LIS202DL 24/36 y axis output data. 7.9 wu_cfg_1 (30h) 7.10 wu_src_1 (31h) table 22. register aoi lir res_1 res_2 yhie ylie xhie xlie table 23. register description aoi and/or combination of interrupt events. default value: 0 (0: or combination of interrupt events; 1: and combination of interrupt events) lir latch interrupt request into wu_src_1 reg with the wu_src_1 reg cleared by reading wu_src_1 reg. default value: 0 (0: interrupt request not latched ; 1: interrupt request latched) res_1 reserved at value: 0. value should not be changed. res_2 reserved at value: 0. value should not be changed. yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) table 24. register -- ia -- -- yh yl xh xl table 25. register description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) yh y high. default value: 0 (0: no interrupt, 1: yh event has occurred) yl y low. default value: 0 (0: no interrupt, 1: yl event has occurred)
LIS202DL register description 25/36 wake-up source register. read only register. reading at this address clears wu_src_1 register and the wu 1 interrupt and allows the refreshment of data in the src_1 register if the latched option was chosen. 7.11 wu_ths_1 (32h) most significant bit (dcrm) is used to select the resetting mode of the duration counter. if dcrm=0 counter is reset when the interrupt is no more active else if dcrm=1 duration counter is decremented. 7.12 wu_duration_1 (33h) duration register for wake-up interrupt 1. duration step and maximum value depend on the odr chosen. step 2.5 msec, from 0 to 637.5 msec if odr=400hz, else step 10 msec, from 0 to 2.55 sec when odr=100hz. the counte r used to implement duration function is blocked when lir=1 in configuration register and the interrupt event is verified xh x high. default value: 0 (0: no interrupt, 1: xh event has occurred) xl x low. default value: 0 (0: no interrupt, 1: xl event has occurred) table 25. register description table 26. register dcrm ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 27. register description dcrm resetting mode selection. default value: 0 (0: counter reset; 1: counter decremented) ths6, ths0 wake-up threshold: default value: 000 0000 table 28. register d7 d6 d5 d4 d3 d2 d1 d0 table 29. register description d7-d0 duration value. default value: 0000 0000
register description LIS202DL 26/36 7.13 wu_cfg_2 (34h) 7.14 wu_src_2 (35h) table 30. register aoi lir res_1 res_2 yhie ylie xhie xlie table 31. register description aoi and/or combination of interrupt events. default value: 0 (0: or combination of interrupt events; 1: and combination of interrupt events) lir latch interrupt request into wu_src _2 reg with the wu_src_2 reg cleared by reading wu_src_2 reg. default value: 0 (0: interrupt request not latched ; 1: interrupt request latched) res_1 reserved at value: 0. value should not be changed. res_2 reserved at value: 0. value should not be changed. yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) table 32. register -- ia -- -- yh yl xh xl table 33. register description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) yh y high. default value: 0 (0: no interrupt; 1: yh event has occurred) yl y low. default value: 0 (0: no interrupt; 1: yl event has occurred)
LIS202DL register description 27/36 wake-up source register. read only register. reading at this address clears wu_src_2 register and the wu_2 interrupt and allows the refreshment of data in the wu_src_2 register if the latched option was chosen. 7.15 wu_ths_2 (36h) most significant bit (dcrm) is used to select the resetting mode of the duration counter. if dcrm=0 counter is reset when the interrupt is no more active else if dcrm=1 duration counter is decremented. 7.16 wu_duration_2 (37h) duration register for wake-up interrupt 2. duration step and maximum value depend on the odr chosen. step 2.5 msec, from 0 to 637.5 msec if odr=400hz, else step 10 msec, from 0 to 2.55 sec when odr=100hz. the counte r used to implement duration function is blocked when lir=1 in configuration register and the interrupt event is verified. xh x high. default value: 0 (0: no interrupt; 1: xh event has occurred) xl x low. default value: 0 (0: no interrupt; 1: xl event has occurred) table 33. register description table 34. register dcrm ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 35. register description dcrm resetting mode selection. default value: 0 (0: counter reset; 1: counter decrements) ths6, ths0 wake-up threshold. default value: 000 0000 table 36. register d7 d6 d5 d4 d3 d2 d1 d0 table 37. register description d7-d0 duration value. default value: 0000 0000
register description LIS202DL 28/36 7.17 click_cfg (38h) table 38. - lir res_1 res_2 double_y single_y double_x single_x table 39. register description lir latch interrupt request into click_s rc reg with the click_src reg refreshed by reading click_src reg. default value: 0 (0: interrupt request not latched; 1: interrupt request latched) res_1 reserved at value: 0. value should not be changed. res_2 reserved at value: 0. value should not be changed. double_y enable interrupt generation on double click event on y axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request) single_y enable interrupt generation on single click event on y axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request) double_x enable interrupt generation on double click event on x axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request) single_x enable interrupt generation on single click event on x axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request) table 40. truth table double_y / x single_y / x click output 000 0 1 single 1 0 double 1 1 single or double
LIS202DL register description 29/36 7.18 click_src (39h) 7.19 click_thsy_x (3bh) from 0.5g(0001) to 7.5g(1111) with step of 0.5g. 7.20 click_timelimit (3dh) from 0 to 127.5msec with step of 0.5 msec. table 41. register -- ia -- -- double_y single_y double_x single_x table 42. register description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) double_y double click on y axis event. default value: 0 (0: no interrupt; 1: double y event has occurred) single_y single click on y axis event.default value: 0 (0: no interrupt; 1: single y event has occurred) double_x double click on x axis event. default value: 0 (0: no interrupt; 1: double x event has occurred) single_x single click on x axis event. default value: 0 (0: no interrupt; 1: single x event has occurred) table 43. register thsy3 thsy2 thsy1 thsy0 thsx3 thsx2 thsx1 thsx0 table 44. register description thsy3, thsy0 click threshold on y axis. default value: 0000 thsx3, thsx0 click threshold on x axis. default value: 0000 table 45. register dur7 dur6 dur5 dur4 dur3 dur2 dur1 dur0
register description LIS202DL 30/36 7.21 click_latency (3eh) from 0 to 255 msec with step of 1 msec. 7.22 click_window (3fh) from 0 to 255 msec with step of 1 msec. table 46. register lat7 lat6 lat5 lat4 lat3 lat2 lat1 lat0 table 47. register win7 win6 win5 win4 win3 win2 win1 win0
LIS202DL typical performance characteristics 31/36 8 typical performance characteristics 8.1 mechanical characteristics at 25c figure 10. x axis 0-g level at 2.5v figure 11. x axis sensitivity at 2.5v figure 12. y axis 0-g level at 2.5v figure 13. y axis sensitivity at 2.5v ?200 ?150 ?100 ?50 0 50 100 150 200 0 5 10 15 20 25 0?g level (mg) percent of parts (%) 16 16.5 17 17.5 18 18.5 19 19.5 20 0 2 4 6 8 10 12 14 16 18 20 sensitivity (mg/digit) percent of parts (%) ?200 ?150 ?100 ?50 0 50 100 150 200 0 5 10 15 20 25 30 35 0?g level (mg) percent of parts (%) 16 16.5 17 17.5 18 18.5 19 19.5 20 0 2 4 6 8 10 12 14 16 18 20 sensitivity (mg/digit) percent of parts (%)
typical performance characteristics LIS202DL 32/36 8.2 mechanical characteristics de rived from measurement in the -40c to +85c temperature range figure 14. x axis 0-g level change vs. temperature at 2.5v figure 15. x axis sensitivity change vs. temperature at 2.5v figure 16. y axis 0-g level change vs. temperature at 2.5v figure 17. y axis sensitivity change vs. temperature at 2.5v ?3 ?2 ?1 0 1 2 3 0 5 10 15 20 25 30 35 0?g level drift (mg/ c) percent of parts (%) ?0.05 0 0.05 0 10 20 30 40 50 60 sensitivity drift (%/deg. c) percent of parts (%) ?3 ?2 ?1 0 1 2 3 0 5 10 15 20 25 30 35 0?g level drift (mg/ c) percent of parts (%) ?0.05 0 0.05 0 10 20 30 40 50 60 sensitivity drift (%/deg. c) percent of parts (%)
LIS202DL typical performance characteristics 33/36 8.3 electro-mechanical ch aracteristics at 25c figure 18. current consumption in normal mode at 2.5v figure 19. current consumption in power down mode at 2.5v 200 250 300 350 400 0 5 10 15 20 25 30 35 current consumption (ua) percent of parts (%) ?1 0 1 2 3 4 5 0 5 10 15 20 25 30 35 current consumption (ua) percent of parts (%)
package information LIS202DL 34/36 9 package information in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 20. lga 14: mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a1 0.920 1.000 0.0362 0.0394 a2 0.700 0.0275 a3 0.180 0.220 0.260 0.0071 0.0087 0.0102 d1 2.850 3.000 3.150 0.1122 0.1181 0.1240 e1 4.850 5.000 5.150 0.1909 0.1968 0.2027 e 0.800 0.0315 d 0.300 0.0118 l1 4.000 0.1575 n 1.360 0.0535 n1 1.200 0.0472 p1 0.965 0.975 0.985 0.0380 0.0384 0.0386 p2 0.640 0.650 0.660 0.0252 0.0256 0.0260 t1 0.750 0.800 0.850 0.0295 0.0315 0.0335 t2 0.450 0.500 0.550 0.0177 0.0197 0.0217 r 1.200 1.600 0.0472 0.0630 h 0.150 0.0059 k 0.050 0.0020 i 0.100 0.0039 s 0.100 0.0039 lga14 (3x5x0.92mm) pitch 0.8mm l and g rid a rray package 7773587 c
LIS202DL revision history 35/36 10 revision history table 48. document revision history date revision changes 11-jun-2007 1 initial release.
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